Principal Packaging Engineer Job at Unity Systems, Santa Clara, CA

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  • Unity Systems
  • Santa Clara, CA

Job Description

Overview

We’re seeking a highly experienced Principal Advanced Packaging Engineer to spearhead the development of cutting-edge semiconductor packaging technologies. This critical role focuses on chiplet integration , high-speed interconnect design , and 2.5D/3D IC packaging solutions for next-generation AI , HPC , and communication systems . You will collaborate across cross-functional teams, from concept to production, to push the boundaries of performance and reliability.

🔧 What You’ll Do

  • Architect and develop advanced IC packaging solutions including flip-chip , TSV , chiplet , and 2.5D/3D stacking for AI and HPC systems.
  • Lead substrate technology innovation using organic , silicon , and glass interposers , optimizing signal integrity , power delivery , and thermal performance .
  • Partner with ASIC design , foundry , and OSAT teams for full-stack integration from BEOL to package-level .
  • Implement and validate high-speed interconnect designs using tools like Cadence , ANSYS , and Siemens NX .
  • Perform electrical, thermal, and mechanical simulations to ensure design reliability and manufacturability.
  • Support reliability testing and failure analysis leveraging techniques such as SEM , TEM , FIB , AFM , and Raman spectroscopy .
  • Apply FMEA , SPC , and DOE methodologies to refine packaging processes and deliver high-yield solutions.
  • Mentor junior engineers and deliver technical training sessions focused on advanced packaging and heterogeneous integration .

What You Bring

  • Master’s degree in Materials Science, Electrical Engineering, or a related technical field.
  • 10+ years of hands-on experience in semiconductor packaging , with a strong focus on chiplet and heterogeneous integration .
  • Deep knowledge of substrate design , high-speed I/O , and BEOL/FEOL integration challenges.
  • Proficiency with industry-standard tools: Siemens NX , Cadence Allegro/Virtuoso , ANSYS , JMP , and ThermoCalc .
  • Expertise in failure analysis and metrology techniques (e.g., SEM, TEM, AFM, XPS).
  • Solid grasp of AI/HPC-specific packaging needs and innovative solution paths.
  • Proven ability to analyze failure modes , identify root causes, and drive corrective actions.

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